A DRAM memory cell of a DRAM circuit typically has a pass transistor connected to a storage capacitor. The DRAM memory cell must dynamically retain a voltage level or charge level within the storage capacitor for a significant period of time in order to sustain a predetermined logic state. There are various combinations of semiconductor manufacturing process methods of assuring that this voltage or charge is retained. A first process method utilizes a processing technique where the capacitance of the storage capacitor of the DRAM memory cell and charge leakage at the junction between the pass transistor and storage capacitor are adequate to sustain a valid logic state for a predetermined period of time. Additionally, a second process method is to provide a threshold voltage for the pass transistor of the DRAM memory cell that is sufficiently high to avoid a charge leakage condition from the storage capacitor of the DRAM memory cell to a common bit line.
A circuit design technique for assuring that the DRAM memory cell maintains a predetermined logic state is to store as much charge on the storage capacitor of the DRAM memory cell as possible. The implementation of this circuit design technique requires that the bit line of the DRAM memory cell be connected to a bit line driver whose output is at a power supply voltage V.sub.DD, and requires a word-line control signal, connected to a control terminal of the pass transistor, be driven to a voltage equal to or above the power supply voltage V.sub.DD plus the threshold voltage of the pass transistor. This technique allows the full V.sub.DD voltage present on the bit line to be connected to the storage capacitor of the DRAM memory cell. Furthermore, the above process and design techniques are commonly utilized in combination in a known DRAM circuit.
There are various circuit techniques which are utilized to generate a word-line voltage that is higher than the normal power supply voltage V.sub.DD. One such circuit technique is to use a charge coupling technique called "bootstrapping" along with a boosted voltage level. Bootstrapping allows the word-line control signal to be boosted above the normal power supply voltage by trapping charge on a gate terminal of a booting transistor when its drain terminal is at a low voltage level, and then to transition the drain terminal voltage of the booting transistor to a boosted voltage level. This action results in capacitively coupling the voltage on the gate terminal of the booting transistor to a voltage which is equal to the change in voltage of the drain terminal of the booting transistor plus the voltage trapped on the gate terminal of the booting transistor. Having the gate terminal of the booting transistor at an elevated voltage permits the boost voltage, connected to the drain terminal of the booting transistor, to be fully transferred to a source terminal of the booting transistor without the normal threshold voltage drop across the booting transistor. However, a primary problem with operating an MOS transistor having small physical dimensions using a boosted voltage is that the boosted voltage may destroy the thin gate oxide or a diffused junction, such as a source or drain junction, during a transistor switching operation. For this reason bootstrapping may not be desirable in an advanced MOS semiconductor manufacturing process.
Another circuit technique is to provide a boosted voltage, which is higher than the standard operating voltage of the DRAM, to a CMOS inverter circuit that drives a word-line signal. A disadvantage to this design approach is that the CMOS transistors that drive the word-line signal must be capable of withstanding the higher operating voltage level during a switching operation, and this is not always possible with an advanced semiconductor manufacturing process.